oscillator
Sensing oscillator and its output conditioning. The Key parts and Ports
columns are generated by docs/gen_hardware_docs.py; edit only the Function
text.
| Sheet | Function | Key parts | Ports |
|---|---|---|---|
differential_ring_oscillator.kicad_sch |
3-stage ring oscillator | 400 Ω, BSS138AKS-QX | EN, Vcc, Vdd, Vout+, Vout- |
oscillator_output_conditioning.kicad_sch |
LVDS receive and divide by 4 | SN65LVDS2DBVR | Vcc, Vdd, Vin+, Vin-, Vout |
clock_divider_by_2.kicad_sch |
Divide-by-2 stage | SN74LVC1G80DCKR | CLK, CLK/2, Vcc, Vdd |
- Each oscillator stage is an
analog/differential_pair.kicad_schwhose tail is fed by oneanalog/full_current_mirror.kicad_schoutput.ENswitches the mirror on through a BSS138. - In
oscillator_output_conditioning, the LVDS receiver recovers the clock fromVin+/Vin-; two cascadedclock_divider_by_2stages give the divided clock onVout.